Effect of Gate-level Design Margin Relaxation on Overall Circuit Performance Metrics in VLSI design

Jae Hoon Kim and Young Hwan Kim



As semiconductor technology scales to the nanometer regime, the variation of process parameters is a critical problem in VLSI design. Thus the need for variation-aware timing analysis for the performance yield is increasing. However, the traditional worst-case corner-based approach gives pessimistic results, and makes meeting given designs specifications difficult. As an alternative to this approach, statistical analysis is proposed as a new and promising variation-aware analysis technique. However, statistical design flow cannot be applied easily to existing design flow, and not enough tools for statistical design exist. To overcome these problems, new design methodology based on traditional static timing analysis (STA) using a relaxed corner proposed nowadays. This paper investigates the effects of corner relaxation on overall circuit performance metrics (yield, power, area) at the gate/transistor levels. Experimental results indicate that if we design the circuit using relaxed corner, though the circuit yield is somewhat reduced, we can get some advantages in area and power aspects.