A Low-Noise Phase-Locked Loop with Programmable Gain VCO

Lip Kai Soh

Altera Corporation


In this paper, a phase-locked loop (PLL) with programmable gain VCO is proposed and analyzed. The proposed design adjusts the gain of the VCO based on the maximum output frequency to achieve lower phase noise. The proposed design is implemented using TSMC 45nm CMOS with a 0.9-V supply voltage. The pre-layout simulation of the proposed PLL architecture shows an improvement of ~30.2% in the RMS jitter compared to the conventional PLL architecture.