In this paper, an adjustable reset pulse phase frequency detector (PFD) for phase-locked loop (PLL) is proposed and analyzed. The proposed PFD adjust the width of the reset pulse when the reference clock and the feedback clock of the PLL are in phase to reduce the static phase error at the PLL output. The proposed PFD is implemented using 45nm CMOS thin oxide device with a 0.9-V supply voltage. A comparison between PLL using proposed PFD architecture and PLL using conventional PFD architecture is done. The pre-layout simulation results show a reduction of ~61% in static phase error when the proposed PFD is implemented on the PLL compared to when the conventional PFD is implemented.