In this paper, first we have demonstrated the suitability of Plackett-Burman Design of Experiment (PB-DOE) method for the sensitivity analysis of a device and a circuit performance to inter- and intra-die process variations. Further, it is shown that PB-DOE method takes relatively less computational time and provides reasonable accuracy as compared to standard Monte Carlo Method. In the next part of the work, computationally efficient methodology for timing yield analysis of standard CMOS cells is proposed. The proposed technique combines well-known statistical methods namely Principal Component Analysis (PCA) and PB-DOE method. Here, the proposed technique is successfully implemented for timing yield estimation of standard CMOS cell implemented in non-planar Double-Gate (DG) FinFET technology. However, our methodology is independent of technology platform and can be implemented on classical bulk CMOS technology or any other emerging technologies too. Furthermore, it is shown that the proposed methodology reduces the computational cost by 35% as compared RSM based Monte Carlo method.