A new charge transfer sense amplifier for low voltage DRAMs is proposed. The proposed charge transfer sense amplifier has two features. One is the double boosting sense node structure, and the other is the dynamic presensing latch. The double boosting sense node structure consists of a main boosting capacitor and an additional boosting capacitor. The boosting capacitors are connected by a PMOS diode-connected transistor. This structure is efficient in generating high sense node voltage in low supply voltage conditions. The dynamic presensing latch is placed at the sensing nodes between the bit-line pair. The dynamic presensing latch enlarges sense node voltage difference (ΔVSA) with safty and robustness. Increased ΔVSA makes pull-down/up latch operation effectively. With a 1.0V power supply voltage using a 0.18um TSMC process, the proposed charge transfer sense amplifier brings a significant increase of about 2.23 times in ΔVSA and a decrease of 74.2% in the sensing delay time compared with the best-known prior scheme.