Product or design quality encompasses many aspects. One of them is the robustness with respect to perturbations. This robustness depends on the implementation technology, but can also be improved at design time. This paper is focused on designs implemented in SRAM-based FPGAs that are sensitive to soft errors in the configuration memory. An approach is proposed to increase the robustness with respect to configuration errors, at no cost, by selectively hardening parts of the design. The selection of locally duplicated functions is made so that the protections take advantage of FPGA resources that would not be used by the implemented design. An automated design flow is presented for Xilinx Virtex V devices and fault injection results show that the design robustness may be noticeably improved without additional cost for a given product.