Crosstalk noise is a critical issue in the deep submicron circuit design, since it causes functional failures in IC chips. This paper proposes an efficient approach to find the timing region of the circuit that timing failure occurs in an IC chip. The proposed method efficiently finds timing failure region by using CGOV metric without iterative simulations. In the experimental results, the proposed method shows 5.4 % average error rate, and 12 % maximum error rate compared with spice simulation results.