In this paper, a robust and energy efficient pulse generator (PG), dedicated to pulse-triggered flip-flops (pulsed-FFs) in ultra-wide voltage range (UWVR) applications, is proposed. Pulsed-FFs are promising candidate for high-speed and low-power applications, thanks to their small data-to-output delay and their shareable PG. However, UWVR circuits work most of the time under the threshold voltage, where local variations lead to a huge spread in logic delays. Therefore, the designers have to ensure that the minimum width of the pulse signal activating the pulsed-FF is large enough to guarantee the correct functionality of the FF. On the other hand, a too large pulse window would lead to an increase of the hold time, and thus energy overhead for inserting delay buffers, which is not acceptable in energy-efficient circuits. This work presents a pulse generator exhibiting excellent performances in the three figures of merit of PGs. Post-layout simulations showed that, for a small area penalty, the robustness of the pulsed-FF is greatly improved.