Path Resistance Reduction through Automated Multi-Level Metal and Via Insertion for IC Layout Design

Thai Lee Lo,  Gregory Sylvester Emmanuel,  Thomas Fong Chee Goh,  Chun Keong Lee,  Joon Heong Ong,  Yng Chuk Tam,  Jonathan Yoong-Seang Ong,  Hui Peng Ong
Spansion Penang Sdn Bhd


Current EDA market has plenty of DFM (Design for Manufacturing) solutions on via doubling for VLSI design which enhances single-level metal (hierarchy) interconnections. A new conceptual approach, Multi-Level Metal and Via (MLMV) is proposed to extend the capability to insert metals and vias across multiple hierarchies to lower effective resistance.

The objective is to improve signal integrity by reducing resistance across metal paths for individual signals, inclusive of supplies across the full chip. MLMV also takes into consideration the critical signals integrity of the design. The tool ensures no metal insertion is too close to critical signals, to prevent potential noise in the design.

The results discussed in this paper show a significant improvement in terms of reducing the effective resistance of experimental test case signal path up to 90% in comparing to the conventional via filling solution. With these significant results, it can be concluded that MLMV is able to populate the metal and via effectively and minimizing resistance in the design.