Eun Ju Hwang1, Wook Kim2, Young Hwan Kim1
1Pohang University of Science and Technology, 2Samsung Electronics
In deterministic timing optimization, timing slack is used to verify whether a timing violation occurs or not without timing updates on the entire circuit. However, in statistical timing optimization, there is currently no criterion to verify whether a timing violation occurs. This paper proposes a novel metric of timing yield slack to verify whether the timing yield violation occurs without updating the timing yield of the entire circuit. This paper also presents an efficient method to compute the proposed timing yield slacks of gates and a strategy to use timing resources for effective statistical optimization. Experimental results on ISCAS-85 benchmark circuits showed that the proposed timing yield slack calculation method has only a 1.89% error on average, and improves the runtime by 460 times as compared with the exact calculation method. Also, the proposed method has a small runtime overhead of 4.85% against the statistical static timing analysis.