Fern Nee Tan1, Sheng Chyan Lee2, Abdul Rahman Faidz2
1Intel Microelectronics, 2Universiti Tunku Abdul Rahman
This paper focuses on the power delivery network (PDN) characterization of high speed IC; particularly focusing on the on-chip capacitance (Cdie). Three packages were used to examine how Cdie would vary when selected power rails were merged on package. The first test package combined power rails which were adjacent to each other, and the second test package combined all common voltage power rails across the entire chip. The Cdie contributed from each I/O buffers as well as Core were measured and compared with the Cdie on the original package design; where all power rails were isolated. It was found that not all the Cdie showed up when power rails were merged. As much as 15% - 44% Cdie was found missing on a merged power rails compare to the original Cdie build in. This paper will describe a methodology to measure and characterize the Cdie, and propose a design guideline to suggest the best way to design a package to ensure that the Cdie is properly leveraged across when a power rail merger is implemented.