Anshul Singh1, Satyam Mandavalli2, Vincent Mooney III3, Keck-Voon Ling4
1International Institute of Information Technology, Hyderabad, India, 2International Institute of Information Techonology, Hyderabad , India, 3Georgia Institute of Technology, USA, 4Nanyang Technological University, Singapore
Quick and accurate error-rate prediction of Probabilistic CMOS (PCMOS) circuits is crucial for their systematic design and performance evaluation. While still in early stage of research, PCMOS has shown potential to drastically reduce energy consumption at a cost of increased errors. Recently, a methodology has been proposed which could predict the error-rates of cascade structures of blocks in PCMOS. It requires error-rates of unique blocks to predict the error-rates of a multi-block cascade structure. The “Three stage model”, which accounts for different noise filtering for different paths in a circuit, has been proposed to characterize unique blocks. While the results obtained from the three stage model produced accurate error-rates for a multi-block cascade structure, the procedure for its characterization is computationally expensive. In this paper, we propose a new method for characterizing the three stage model that not only provides accurate results but is also computationally cheap.