Amit Vishnani, Marshnil Dave, Maryam Baghini, Dinesh Sharma
IIT Bombay
On-chip test circuits are key components for testing of sophisticated System on Chips (SoCs). This paper presents a fully on-chip test system to characterize high-speed on-chip interconnects. It measures the maximum data-rate at which an on-chip interconnect scheme can work (throughput). The proposed system is based on signature analysis technique. The components of the proposed system are chosen such that it can handle Bit Error Rate (BER) of the order of 10-8. The test system is designed and laid out in 180 nm CMOS technology. It can characterize the interconnect operating at data rates as high as 1.66 Gbps even in the worst process corner. Simulations using the device parameters measured from a test chip made in the same technology indicate that the measurable throughput by the proposed test system is 1.85 Gbps for that run. Even in the presence of temperature variations, the proposed system can handle highest possible throughput of the interconnects.