Jackson Kong, Bok Eng Cheah, Shanggar Periaman, Kooi Chi Ooi
Intel Malaysia
This paper presents a novel enabling technique exploiting interposer approach such as silicon and package interposer in the area of package-on-package (PoP) technology to achieve ultra small form factor packaging solution. The electrical performance of such interconnect innovation is discussed in this paper, and pitted against the conventional PoP methods using solder ball connection, as well as the recent developed over-molded interconnection technology. This paper also highlights the advantages of the aforementioned silicon and package interposer technology from electrical performance perspective such as signal integrity in terms of impedance matching, noise shielding, electrical return and insertion losses, of which modeling and simulation data are presented. Other attributes e.g. device input-output (IO) density and physical scalability associated with the above inter-package connection systems are also compared and further elaborated in this paper.