Mei Yee Ng
MIMOS Berhad
This paper presents a 0.18um process Successive-Approximation Register Analog-to-Digital Converter (SAR ADC) design that can operate at a low voltage of minimum 1.4V across process corners and temperature with the power consumption of less than 100uW. The design comprises three main blocks namely a fully differential latched comparator, binary-weighted capacitors Digital-to-Analog Converter (DAC) and a SAR digital control logic module. The SAR ADC was designed to work at a minimum of 1.4V to cater to the 1.5V AA-battery +/-10% and accepts a maximum clock frequency of 500kHz. In order to reduce the current consumption, this design uses the capacitors in the DAC as the sample-and-hold (S/H) component, together with a hybrid DAC architecture. The pre-amp used before the comparator has folded-cascode configuration to enable it to work at a low voltage level and differential outputs to account for noise cancellation. This circuit was designed using Silterra C18G 0.18um process.